An impedance control PCB is a board where specific traces are manufactured to maintain a precise characteristic impedance value, typically 50 ohms for single-ended signals or 100 ohms for differential pairs. At low frequencies and slow data rates, the impedance of a PCB trace is not important. A trace is simply a conductor connecting two points. At high frequencies and fast data rates, every trace behaves as a transmission line, and if the impedance of that transmission line does not match the impedance of the driver and receiver, a portion of the signal is reflected back toward the source. Those reflections cause signal distortion, timing errors, and EMI problems that get worse as data rates and frequencies increase.
Controlled impedance is no longer a concern only for RF engineers working with microwave circuits. It is now a standard requirement for USB 3.0, PCIe, DDR4 and DDR5 memory interfaces, HDMI, Ethernet at 1 Gbps and above, MIPI, and any other high-speed digital interface running above a few hundred megabits per second. If your design contains any of these interfaces, impedance control is not optional.
This article explains how PCB impedance works, what determines it, how manufacturers control and verify it, and what you need to include in your design files to get a correctly built controlled impedance board.
What Characteristic Impedance Means on a PCB
Characteristic impedance is not the same as DC resistance. A copper trace has very low DC resistance, typically milliohms per centimeter. Characteristic impedance is an AC property that describes how the trace interacts with high-frequency signals. It is determined by the geometry of the trace and the electrical properties of the surrounding materials, not by the copper resistivity.
When a signal travels along a PCB trace at high speed, it creates an electromagnetic wave that propagates along the trace guided by the copper and the dielectric material surrounding it. The characteristic impedance of the trace is the ratio of the voltage wave to the current wave at any point along that transmission line. It is determined by the distributed capacitance and inductance per unit length of the trace geometry.
If the source driving the trace has an output impedance of 50 ohms and the trace has a characteristic impedance of 50 ohms and the receiver input is also 50 ohms, the signal travels from source to load with no reflections. The entire signal reaches the receiver. If the trace impedance is 75 ohms instead of 50 ohms, the mismatch causes a reflected wave that travels back toward the source, arrives with a delay relative to the original signal, and distorts the waveform at the source. At high data rates, this reflection overlaps with subsequent bits and causes bit errors.
The Six Factors That Determine PCB Trace Impedance
Every trace on a PCB has a characteristic impedance that is set by six physical parameters. Controlled impedance manufacturing means controlling these parameters to hold the trace impedance within a specified tolerance of the target value.
Trace width
Wider traces have lower characteristic impedance. Narrower traces have higher impedance. This is the most commonly adjusted parameter for hitting an impedance target because it is directly controlled by the PCB imaging and etching process. A 1 mil change in trace width on a typical 50 ohm microstrip trace causes approximately a 2 to 3 ohm shift in impedance depending on the stack-up. FastTurn PCB controls trace width to within plus or minus 0.5 mil on controlled impedance builds, which keeps impedance variation within the target tolerance for most stack-up configurations.
Dielectric thickness
The distance between the signal trace and its reference plane determines how strongly the electric field couples between them. Greater dielectric thickness increases impedance for a given trace width. Thinner dielectric decreases it. Dielectric thickness in a multilayer board is set by the prepreg and core materials selected for the stack-up. It varies slightly across the panel due to resin flow during lamination, which is one source of impedance variation that careful lamination process control minimizes. FastTurn PCB uses premium laminate materials with controlled thickness specifications and applies lamination process controls to maintain dielectric thickness uniformity.
Dielectric constant of the laminate
The dielectric constant of the material between the trace and the reference plane directly affects trace impedance. Higher Dk materials lower impedance for a given trace geometry. Lower Dk materials raise it. Standard FR4 has a Dk of approximately 4.2 to 4.5 depending on glass weave and frequency. Rogers RO4003C has a Dk of 3.55. PTFE materials can be as low as 2.2. The Dk value you use in your impedance calculation must match the actual Dk of the laminate at your operating frequency. Using the nominal low-frequency Dk for a design that operates at 5 GHz will produce an impedance that differs from the calculated value because FR4 Dk decreases as frequency increases.
Copper thickness
The effect is smaller than trace width or dielectric thickness, but it is measurable. Standard 1 oz copper (35 micrometers finished) is the most common specification. 0.5 oz copper is used on fine-line inner layers. 2 oz copper is used for high current traces. When calculating impedance, use the actual finished copper thickness after plating, not the nominal foil weight, because plating adds copper during through-hole metallization.
Trace spacing for differential pairs
For differential pairs, the spacing between the positive and negative traces determines the coupling between them, which sets the differential impedance. Tighter spacing increases coupling and reduces differential impedance. Wider spacing reduces coupling and increases differential impedance. Both traces must have equal width and equal spacing from the reference plane throughout their routing to maintain balanced impedance and minimize common-mode noise conversion.
Soldermask thickness
Printed soldermask over a trace slightly reduces its impedance. FastTurn PCB data shows that a single soldermask coat reduces single-ended impedance by approximately 2 ohms and differential impedance by approximately 8 ohms. A second coat doubles this effect. This is why impedance calculations for outer-layer traces should account for soldermask when the traces will be covered, and why some RF designs specify that soldermask is not applied over controlled impedance traces.
Transmission Line Structures Used for Controlled Impedance
The physical arrangement of the trace relative to reference planes determines which transmission line structure it forms. Each structure has a different impedance formula, and each has different applications.
Microstrip
A microstrip is a trace on the outer layer of the board with a solid reference plane on the layer immediately below it. The trace is exposed to air on top and sits on the dielectric above the reference plane. Microstrip is the simplest controlled impedance structure. It is easy to route, easy to probe, and relatively easy to rework if needed. The characteristic impedance of a microstrip is a function of trace width, dielectric thickness, dielectric constant, and copper thickness. For a 50 ohm target on a standard 4 mil FR4 dielectric with 1 oz copper, the required trace width is approximately 7 to 8 mil depending on the exact Dk.
Microstrip is the standard structure for single-ended RF signals on outer layers, including antenna feeds, SMA connector traces, and board-level RF interconnects.
Stripline
A stripline is a trace sandwiched between two reference planes on inner layers of the board. The trace is completely surrounded by dielectric material with reference planes above and below. Stripline provides better EMI shielding than microstrip because the signal is enclosed between ground planes. It also offers more consistent impedance because the dielectric environment is uniform on all sides, unlike microstrip where the top surface faces air.
The tradeoff is that stripline requires narrower traces than microstrip to achieve the same impedance target, because the two reference planes together provide stronger coupling. For a 50 ohm stripline in a standard stack-up, trace widths in the 4 to 5 mil range are typical on inner layers. Stripline is used for high-speed digital signals on inner layers where EMI control and impedance consistency across the board are more important than ease of routing or probing.
Coplanar waveguide
A coplanar waveguide is a trace on an outer layer with ground copper poured adjacent to the trace on the same layer, separated by a controlled gap. The ground copper on either side of the trace provides additional field confinement beyond what the underlying reference plane provides. Coplanar waveguide is used for very high frequency traces on outer layers, particularly in RF and microwave circuit boards, because the tight field confinement reduces radiation loss and makes the structure less sensitive to board thickness variation. Grounded coplanar waveguide adds a reference plane below the coplanar structure for even better performance.
Differential pair structures
Both microstrip and stripline can be routed as differential pairs. The two traces of a pair carry equal and opposite signals. Common-mode noise picked up equally on both traces cancels at the differential receiver, which is one of the primary reasons differential signaling is used for high-speed interfaces in noisy environments. Differential impedance is typically 100 ohms for most digital interfaces (USB, PCIe, HDMI, Ethernet) and 90 ohms for some legacy interfaces. It is set by the individual trace width, the spacing between traces, and the coupling from the reference plane, and must be verified by TDR measurement of the actual fabricated structure.
How Manufacturers Control and Verify Impedance
Controlled impedance is not achieved by calculation alone. Calculation gives you the trace geometry needed to hit a target, but the actual impedance of the fabricated board depends on how well the manufacturer controls the six physical parameters described above across the production panel. Verification by measurement is the only way to confirm that the fabricated board meets the specification.
Stack-up control
The first step in controlled impedance manufacturing is a validated stack-up. FastTurn PCB maintains tested stack-up templates for common layer counts and dielectric thicknesses. For each stack-up, the actual Dk values of the specific laminate materials used are known, and the dielectric thicknesses after lamination are characterized. When you specify a controlled impedance requirement, engineers use these validated parameters to calculate the trace width needed to hit your target and confirm the calculation during DFM review.
Imaging and etch control
Trace width is controlled during the imaging and etching process. FastTurn PCB uses Orbotech Laser Direct Imaging systems for inner and outer layer imaging. LDI exposes the photoresist directly from Gerber data, achieving trace width tolerance within plus or minus 0.5 mil across the panel. Etch chemistry, etch time, and etchant temperature are monitored and controlled to maintain consistent etch factor across production. Process compensation is applied to the Gerber data during CAM processing to account for the known etch undercut, so the finished trace width after etching matches the target.
TDR testing on impedance coupons
Every controlled impedance order at FastTurn PCB includes TDR testing on test coupons included in the production panel. A test coupon is a straight trace of the same geometry as your controlled impedance traces, placed on the panel edge outside the board outline. After fabrication, a TDR instrument applies a fast electrical pulse to the coupon and measures the reflected signal to calculate the actual impedance along the trace length.
TDR testing is the standard method for verifying controlled impedance in PCB production. Measuring the actual signal traces on your board would require cutting into it, which is not practical. The coupon provides an identical trace geometry without damaging your boards. FastTurn PCB holds controlled impedance to within plus or minus 5 ohms or plus or minus 10 percent, with TDR test reports shipped with every controlled impedance order. An optional tighter tolerance of plus or minus 5 percent is available for designs requiring more precise impedance control.
Cross-section analysis
For orders where verification of dielectric thickness or copper plating is required, cross-section inspection cuts through the board at a specific location and measures the actual layer dimensions under a microscope. This is particularly useful for verifying via plating quality on HDI boards or confirming dielectric thickness on high-frequency laminates. FastTurn PCB offers microsection analysis as an option on all controlled impedance orders.
What Interfaces Require Controlled Impedance
The list of digital interfaces that require controlled impedance has grown steadily as data rates have increased. If your design includes any of the following, controlled impedance is a requirement:
- USB 2.0: 90 ohm differential impedance on the D+ and D- pair. Required for all USB 2.0 designs operating at high-speed (480 Mbps) or full-speed (12 Mbps).
- USB 3.0, 3.1, and 3.2: 90 ohm differential impedance on SuperSpeed pairs. Required for all high-speed USB designs. Controlled impedance and length matching are critical for reliable operation at 5, 10, and 20 Gbps.
- PCIe Gen 1 through Gen 5: 85 ohm differential impedance on transmit and receive pairs. PCIe Gen 4 at 16 Gbps and Gen 5 at 32 Gbps are very sensitive to impedance discontinuities, via stubs, and length mismatch.
- DDR4 and DDR5 memory interfaces: 50 ohm single-ended for address and control signals, 100 ohm differential for clock and data strobe pairs. DDR5 at 6400 MT/s requires tight length matching within groups as well as controlled impedance.
- HDMI 1.4 and 2.0: 100 ohm differential on TMDS data and clock pairs. HDMI 2.1 at 48 Gbps has even tighter requirements and may require low-loss materials on the signal layers.
- Gigabit Ethernet and 10GbE: 100 ohm differential on the differential pairs. 10GbE on FR4 requires tight impedance control and preferably low-loss or halogen-free laminate to manage insertion loss over longer trace lengths.
- MIPI CSI and DSI: 100 ohm differential on high-speed data lanes. Common in camera and display interfaces in mobile and embedded applications.
- RF and microwave signals: 50 ohm single-ended for RF signals above 500 MHz. Rogers or other low-loss laminates are typically required above 2 GHz for designs with tight insertion loss budgets.
How to Specify Controlled Impedance in Your Design Files
Clear impedance specifications in your design documentation are the most important thing you can provide for a controlled impedance order. Ambiguous or incomplete specifications are the most common cause of impedance problems on delivered boards.
Identify controlled impedance nets clearly
List every net or group of nets that requires controlled impedance in your fabrication notes or a separate impedance specification document. Specify the target impedance value, the tolerance, the transmission line structure (microstrip, stripline, or differential pair), and the layer on which each net is routed. A useful convention is to use a trace width like 5.1 mil instead of 5.0 mil for controlled impedance traces, which helps the manufacturer instantly identify them during CAM review.
Provide a complete stack-up document
Your stack-up document should define every layer: layer number, function (signal, power, or ground), copper weight, dielectric material and nominal thickness, and finished board thickness. For controlled impedance, also specify the Dk value you used in your calculations, the target trace width, and the reference layer for each controlled impedance specification. This document lets the manufacturer verify your trace geometry calculation and adjust the production trace width to compensate for their specific laminate properties if needed.
Include TDR test coupons in your Gerber data
TDR coupons are straight-line traces on the panel edge outside the board outline. Include at least one coupon per distinct impedance specification on each signal layer. The standard coupon length is 150 mm. Include a reference ground trace adjacent to each single-ended coupon, and include both traces of a differential pair at their production spacing for differential impedance coupons. Without coupons in your panel data, the manufacturer cannot perform TDR testing on your specific trace geometry.
Specify soldermask treatment for RF traces
If your design has outer-layer RF or microwave traces where soldermask over the trace would shift impedance outside your tolerance, specify in your fabrication notes that soldermask is to be pulled back from those traces. Include the controlled impedance net names or reference designators so the CAM engineer can identify which traces are affected.
Confirm with your manufacturer during DFM
Before production starts, confirm with your manufacturer that the trace width in your Gerber data will produce the specified impedance on their specific stack-up. A good controlled impedance manufacturer will review your calculation during DFM and adjust the production trace width within your tolerance if their tested laminate parameters differ from your assumed values. FastTurn PCB performs this review on every controlled impedance order and provides feedback before production begins.
Common Controlled Impedance Problems and How to Prevent Them
Impedance too high or too low across the whole board
This indicates a systematic error in the stack-up or trace width. The most common causes are using a Dk value in your calculation that does not match the actual laminate, using a dielectric thickness that differs from the actual pressed thickness, or failing to account for process compensation in your trace width. Prevention: confirm your stack-up parameters with your manufacturer during DFM before production.
Impedance varies along the length of a trace
Variation along a trace indicates local trace width changes caused by layout features such as bends, vias, pad necking, or copper pours adjacent to the trace. Even a small intrusion of a ground pour within 3 to 5 mil of a controlled impedance trace affects its coupling and shifts local impedance. Prevention: maintain consistent clearance from all copper features to controlled impedance traces. Avoid 90 degree bends on high-frequency traces. Use a consistent reference plane with no splits or voids under controlled impedance traces.
Differential pair imbalance
An imbalanced differential pair occurs when the positive and negative traces have unequal widths, unequal lengths, or unequal spacing from the reference plane. The result is increased common-mode noise and degraded rejection of common-mode interference. Prevention: route differential pairs with equal trace widths set by your impedance target, keep traces tightly coupled throughout their length, match lengths within the pair to your interface specification, and avoid routing the pair across ground plane splits.
Via discontinuities on high-speed signals
Every via transition on a high-speed signal creates a small impedance discontinuity. The via barrel has different capacitance and inductance than the trace, and the via stub below the last connected layer causes resonant reflections at frequencies where the stub is a significant fraction of a quarter wavelength. Prevention: minimize via transitions on high-speed signal paths. For designs above 5 GHz, use back-drilling to remove via stubs. Use void keepouts under controlled impedance traces to prevent ground pour intrusion.
Controlled Impedance Tolerances at FastTurn PCB
FastTurn PCB offers two tolerance options for controlled impedance production:
- Standard tolerance: plus or minus 10 percent of the target impedance value. This is the appropriate specification for most digital interfaces including USB, PCIe, DDR, Ethernet, and HDMI where interface standards define the acceptable impedance range.
- Tight tolerance: plus or minus 5 percent of the target impedance value. Available for RF and microwave applications, precision analog circuits, and any design where tighter impedance control is required by the application specification.
- Optional tightest tolerance: plus or minus 5 ohms absolute. Used for demanding RF applications where percentage tolerance does not adequately constrain impedance at low target values.
All controlled impedance orders include TDR testing on panel coupons and a test report shipped with the boards. The report shows the measured impedance at multiple points along the coupon and confirms whether the result falls within the specified tolerance.
Working with FastTurn PCB on Controlled Impedance Projects
FastTurn PCB has built controlled impedance PCBs for customers across digital computing, 5G infrastructure, automotive electronics, medical devices, and RF applications since 2015. Every controlled impedance order starts with a free DFM review. Engineers verify your stack-up parameters against your impedance calculations, check your trace width against their tested laminate Dk values, confirm that TDR coupons are included in your panel data, and flag any layout features that could cause local impedance variation.
Controlled impedance builds are available on FR4, high Tg FR4, halogen-free laminates, Rogers RO4003C and RO4350B, and other specialty materials. Prototype builds on standard materials with controlled impedance ship in 3 to 5 business days. High frequency builds on Rogers materials with controlled impedance and TDR verification ship in 2 to 3 business days for simple builds, and 5 to 7 days for multilayer configurations.
Certifications: ISO 9001, ISO 13485, UL, RoHS, REACH. Boards inspected to IPC-A-600 and IPC-6012. Assemblies to IPC-A-610 Class 2 or Class 3. There is no minimum order quantity.
Conclusion
Controlled impedance is required for any PCB carrying high-speed digital or RF signals. The six physical parameters that determine trace impedance, trace width, dielectric thickness, dielectric constant, copper thickness, trace spacing, and soldermask, must all be controlled and verified by measurement during production. A calculation is not enough.
Getting a correctly built controlled impedance board depends on clear specification in your design files, a validated stack-up that your manufacturer understands and works with regularly, TDR test coupons included in your panel, and a manufacturing partner who reviews your impedance calculations before production begins and provides measured test results with the shipment.
To get a free DFM review and quote for your next controlled impedance design, visit impedance control PCB fabrication at FastTurn PCB and upload your Gerber files for a same-day engineering review.
